main
1// Code generated by command: go run asm.go -out ../ubc_amd64.s -pkg ubc. DO NOT EDIT.
2
3//go:build !noasm && gc && amd64
4
5#include "textflag.h"
6
7// func CalculateDvMaskAMD64(W [80]uint32) uint32
8TEXT ยทCalculateDvMaskAMD64(SB), NOSPLIT, $0-324
9 MOVL $0xffffffff, AX
10
11 // (((((W[44] ^ W[45]) >> 29) & 1) - 1) | ^(DV_I_48_0_bit | DV_I_51_0_bit | DV_I_52_0_bit | DV_II_45_0_bit | DV_II_46_0_bit | DV_II_50_0_bit | DV_II_51_0_bit))
12 MOVL W_44+176(FP), CX
13 MOVL W_45+180(FP), DX
14 XORL DX, CX
15 SHRL $0x1d, CX
16 ANDL $0x00000001, CX
17 DECL CX
18 ORL $0xfd7c5f7f, CX
19 ANDL CX, AX
20
21 // mask &= (((((W[49] ^ W[50]) >> 29) & 1) - 1) | ^(DV_I_46_0_bit | DV_II_45_0_bit | DV_II_50_0_bit | DV_II_51_0_bit | DV_II_55_0_bit | DV_II_56_0_bit))
22 MOVL W_49+196(FP), CX
23 MOVL W_50+200(FP), DX
24 XORL DX, CX
25 SHRL $0x1d, CX
26 ANDL $0x00000001, CX
27 DECL CX
28 ORL $0x3d7efff7, CX
29 ANDL CX, AX
30
31 // mask &= (((((W[48] ^ W[49]) >> 29) & 1) - 1) | ^(DV_I_45_0_bit | DV_I_52_0_bit | DV_II_49_0_bit | DV_II_50_0_bit | DV_II_54_0_bit | DV_II_55_0_bit))
32 MOVL W_48+192(FP), CX
33 MOVL W_49+196(FP), DX
34 XORL DX, CX
35 SHRL $0x1d, CX
36 ANDL $0x00000001, CX
37 DECL CX
38 ORL $0x9f5f7ffb, CX
39 ANDL CX, AX
40
41 // mask &= ((((W[47] ^ (W[50] >> 25)) & (1 << 4)) - (1 << 4)) | ^(DV_I_47_0_bit | DV_I_49_0_bit | DV_I_51_0_bit | DV_II_45_0_bit | DV_II_51_0_bit | DV_II_56_0_bit))
42 MOVL W_47+188(FP), CX
43 MOVL W_50+200(FP), DX
44 SHRL $0x19, DX
45 XORL DX, CX
46 ANDL $0x00000010, CX
47 SUBL $0x00000010, CX
48 ORL $0x7dfedddf, CX
49 ANDL CX, AX
50
51 // mask &= (((((W[47] ^ W[48]) >> 29) & 1) - 1) | ^(DV_I_44_0_bit | DV_I_51_0_bit | DV_II_48_0_bit | DV_II_49_0_bit | DV_II_53_0_bit | DV_II_54_0_bit))
52 MOVL W_47+188(FP), CX
53 MOVL W_48+192(FP), DX
54 XORL DX, CX
55 SHRL $0x1d, CX
56 ANDL $0x00000001, CX
57 DECL CX
58 ORL $0xcfcfdffd, CX
59 ANDL CX, AX
60
61 // mask &= (((((W[46] >> 4) ^ (W[49] >> 29)) & 1) - 1) | ^(DV_I_46_0_bit | DV_I_48_0_bit | DV_I_50_0_bit | DV_I_52_0_bit | DV_II_50_0_bit | DV_II_55_0_bit))
62 MOVL W_46+184(FP), CX
63 SHRL $0x04, CX
64 MOVL W_49+196(FP), DX
65 SHRL $0x1d, DX
66 XORL DX, CX
67 ANDL $0x00000001, CX
68 DECL CX
69 ORL $0xbf7f7777, CX
70 ANDL CX, AX
71
72 // mask &= (((((W[46] ^ W[47]) >> 29) & 1) - 1) | ^(DV_I_43_0_bit | DV_I_50_0_bit | DV_II_47_0_bit | DV_II_48_0_bit | DV_II_52_0_bit | DV_II_53_0_bit))
73 MOVL W_46+184(FP), CX
74 MOVL W_47+188(FP), DX
75 XORL DX, CX
76 SHRL $0x1d, CX
77 ANDL $0x00000001, CX
78 DECL CX
79 ORL $0xe7e7f7fe, CX
80 ANDL CX, AX
81
82 // mask &= (((((W[45] >> 4) ^ (W[48] >> 29)) & 1) - 1) | ^(DV_I_45_0_bit | DV_I_47_0_bit | DV_I_49_0_bit | DV_I_51_0_bit | DV_II_49_0_bit | DV_II_54_0_bit))
83 MOVL W_45+180(FP), CX
84 SHRL $0x04, CX
85 MOVL W_48+192(FP), DX
86 SHRL $0x1d, DX
87 XORL DX, CX
88 ANDL $0x00000001, CX
89 DECL CX
90 ORL $0xdfdfdddb, CX
91 ANDL CX, AX
92
93 // mask &= (((((W[45] ^ W[46]) >> 29) & 1) - 1) | ^(DV_I_49_0_bit | DV_I_52_0_bit | DV_II_46_0_bit | DV_II_47_0_bit | DV_II_51_0_bit | DV_II_52_0_bit))
94 MOVL W_45+180(FP), CX
95 MOVL W_46+184(FP), DX
96 XORL DX, CX
97 SHRL $0x1d, CX
98 ANDL $0x00000001, CX
99 DECL CX
100 ORL $0xf5f57dff, CX
101 ANDL CX, AX
102
103 // mask &= (((((W[44] >> 4) ^ (W[47] >> 29)) & 1) - 1) | ^(DV_I_44_0_bit | DV_I_46_0_bit | DV_I_48_0_bit | DV_I_50_0_bit | DV_II_48_0_bit | DV_II_53_0_bit))
104 MOVL W_44+176(FP), CX
105 SHRL $0x04, CX
106 MOVL W_47+188(FP), DX
107 SHRL $0x1d, DX
108 XORL DX, CX
109 ANDL $0x00000001, CX
110 DECL CX
111 ORL $0xefeff775, CX
112 ANDL CX, AX
113
114 // mask &= (((((W[43] >> 4) ^ (W[46] >> 29)) & 1) - 1) | ^(DV_I_43_0_bit | DV_I_45_0_bit | DV_I_47_0_bit | DV_I_49_0_bit | DV_II_47_0_bit | DV_II_52_0_bit))
115 MOVL W_43+172(FP), CX
116 SHRL $0x04, CX
117 MOVL W_46+184(FP), DX
118 SHRL $0x1d, DX
119 XORL DX, CX
120 ANDL $0x00000001, CX
121 DECL CX
122 ORL $0xf7f7fdda, CX
123 ANDL CX, AX
124
125 // mask &= (((((W[43] ^ W[44]) >> 29) & 1) - 1) | ^(DV_I_47_0_bit | DV_I_50_0_bit | DV_I_51_0_bit | DV_II_45_0_bit | DV_II_49_0_bit | DV_II_50_0_bit))
126 MOVL W_43+172(FP), CX
127 MOVL W_44+176(FP), DX
128 XORL DX, CX
129 SHRL $0x1d, CX
130 ANDL $0x00000001, CX
131 DECL CX
132 ORL $0xff5ed7df, CX
133 ANDL CX, AX
134
135 // mask &= (((((W[42] >> 4) ^ (W[45] >> 29)) & 1) - 1) | ^(DV_I_44_0_bit | DV_I_46_0_bit | DV_I_48_0_bit | DV_I_52_0_bit | DV_II_46_0_bit | DV_II_51_0_bit))
136 MOVL W_42+168(FP), CX
137 SHRL $0x04, CX
138 MOVL W_45+180(FP), DX
139 SHRL $0x1d, DX
140 XORL DX, CX
141 ANDL $0x00000001, CX
142 DECL CX
143 ORL $0xfdfd7f75, CX
144 ANDL CX, AX
145
146 // mask &= (((((W[41] >> 4) ^ (W[44] >> 29)) & 1) - 1) | ^(DV_I_43_0_bit | DV_I_45_0_bit | DV_I_47_0_bit | DV_I_51_0_bit | DV_II_45_0_bit | DV_II_50_0_bit))
147 MOVL W_41+164(FP), CX
148 SHRL $0x04, CX
149 MOVL W_44+176(FP), DX
150 SHRL $0x1d, DX
151 XORL DX, CX
152 ANDL $0x00000001, CX
153 DECL CX
154 ORL $0xff7edfda, CX
155 ANDL CX, AX
156
157 // mask &= (((((W[40] ^ W[41]) >> 29) & 1) - 1) | ^(DV_I_44_0_bit | DV_I_47_0_bit | DV_I_48_0_bit | DV_II_46_0_bit | DV_II_47_0_bit | DV_II_56_0_bit))
158 MOVL W_40+160(FP), CX
159 MOVL W_41+164(FP), DX
160 XORL DX, CX
161 SHRL $0x1d, CX
162 ANDL $0x00000001, CX
163 DECL CX
164 ORL $0x7ff5ff5d, CX
165 ANDL CX, AX
166
167 // mask &= (((((W[54] ^ W[55]) >> 29) & 1) - 1) | ^(DV_I_51_0_bit | DV_II_47_0_bit | DV_II_50_0_bit | DV_II_55_0_bit | DV_II_56_0_bit))
168 MOVL W_54+216(FP), CX
169 MOVL W_55+220(FP), DX
170 XORL DX, CX
171 SHRL $0x1d, CX
172 ANDL $0x00000001, CX
173 DECL CX
174 ORL $0x3f77dfff, CX
175 ANDL CX, AX
176
177 // mask &= (((((W[53] ^ W[54]) >> 29) & 1) - 1) | ^(DV_I_50_0_bit | DV_II_46_0_bit | DV_II_49_0_bit | DV_II_54_0_bit | DV_II_55_0_bit))
178 MOVL W_53+212(FP), CX
179 MOVL W_54+216(FP), DX
180 XORL DX, CX
181 SHRL $0x1d, CX
182 ANDL $0x00000001, CX
183 DECL CX
184 ORL $0x9fddf7ff, CX
185 ANDL CX, AX
186
187 // mask &= (((((W[52] ^ W[53]) >> 29) & 1) - 1) | ^(DV_I_49_0_bit | DV_II_45_0_bit | DV_II_48_0_bit | DV_II_53_0_bit | DV_II_54_0_bit))
188 MOVL W_52+208(FP), CX
189 MOVL W_53+212(FP), DX
190 XORL DX, CX
191 SHRL $0x1d, CX
192 ANDL $0x00000001, CX
193 DECL CX
194 ORL $0xcfeefdff, CX
195 ANDL CX, AX
196
197 // mask &= ((((W[50] ^ (W[53] >> 25)) & (1 << 4)) - (1 << 4)) | ^(DV_I_50_0_bit | DV_I_52_0_bit | DV_II_46_0_bit | DV_II_48_0_bit | DV_II_54_0_bit))
198 MOVL W_50+200(FP), CX
199 MOVL W_53+212(FP), DX
200 SHRL $0x19, DX
201 XORL DX, CX
202 ANDL $0x00000010, CX
203 SUBL $0x00000010, CX
204 ORL $0xdfed77ff, CX
205 ANDL CX, AX
206
207 // mask &= (((((W[50] ^ W[51]) >> 29) & 1) - 1) | ^(DV_I_47_0_bit | DV_II_46_0_bit | DV_II_51_0_bit | DV_II_52_0_bit | DV_II_56_0_bit))
208 MOVL W_50+200(FP), CX
209 MOVL W_51+204(FP), DX
210 XORL DX, CX
211 SHRL $0x1d, CX
212 ANDL $0x00000001, CX
213 DECL CX
214 ORL $0x75fdffdf, CX
215 ANDL CX, AX
216
217 // mask &= ((((W[49] ^ (W[52] >> 25)) & (1 << 4)) - (1 << 4)) | ^(DV_I_49_0_bit | DV_I_51_0_bit | DV_II_45_0_bit | DV_II_47_0_bit | DV_II_53_0_bit))
218 MOVL W_49+196(FP), CX
219 MOVL W_52+208(FP), DX
220 SHRL $0x19, DX
221 XORL DX, CX
222 ANDL $0x00000010, CX
223 SUBL $0x00000010, CX
224 ORL $0xeff6ddff, CX
225 ANDL CX, AX
226
227 // mask &= ((((W[48] ^ (W[51] >> 25)) & (1 << 4)) - (1 << 4)) | ^(DV_I_48_0_bit | DV_I_50_0_bit | DV_I_52_0_bit | DV_II_46_0_bit | DV_II_52_0_bit))
228 MOVL W_48+192(FP), CX
229 MOVL W_51+204(FP), DX
230 SHRL $0x19, DX
231 XORL DX, CX
232 ANDL $0x00000010, CX
233 SUBL $0x00000010, CX
234 ORL $0xf7fd777f, CX
235 ANDL CX, AX
236
237 // mask &= (((((W[42] ^ W[43]) >> 29) & 1) - 1) | ^(DV_I_46_0_bit | DV_I_49_0_bit | DV_I_50_0_bit | DV_II_48_0_bit | DV_II_49_0_bit))
238 MOVL W_42+168(FP), CX
239 MOVL W_43+172(FP), DX
240 XORL DX, CX
241 SHRL $0x1d, CX
242 ANDL $0x00000001, CX
243 DECL CX
244 ORL $0xffcff5f7, CX
245 ANDL CX, AX
246
247 // mask &= (((((W[41] ^ W[42]) >> 29) & 1) - 1) | ^(DV_I_45_0_bit | DV_I_48_0_bit | DV_I_49_0_bit | DV_II_47_0_bit | DV_II_48_0_bit))
248 MOVL W_41+164(FP), CX
249 MOVL W_42+168(FP), DX
250 XORL DX, CX
251 SHRL $0x1d, CX
252 ANDL $0x00000001, CX
253 DECL CX
254 ORL $0xffe7fd7b, CX
255 ANDL CX, AX
256
257 // mask &= (((((W[40] >> 4) ^ (W[43] >> 29)) & 1) - 1) | ^(DV_I_44_0_bit | DV_I_46_0_bit | DV_I_50_0_bit | DV_II_49_0_bit | DV_II_56_0_bit))
258 MOVL W_40+160(FP), CX
259 MOVL W_43+172(FP), DX
260 SHRL $0x04, CX
261 SHRL $0x1d, DX
262 XORL DX, CX
263 ANDL $0x00000001, CX
264 DECL CX
265 ORL $0x7fdff7f5, CX
266 ANDL CX, AX
267
268 // mask &= (((((W[39] >> 4) ^ (W[42] >> 29)) & 1) - 1) | ^(DV_I_43_0_bit | DV_I_45_0_bit | DV_I_49_0_bit | DV_II_48_0_bit | DV_II_55_0_bit))
269 MOVL W_39+156(FP), CX
270 MOVL W_42+168(FP), DX
271 SHRL $0x04, CX
272 SHRL $0x1d, DX
273 XORL DX, CX
274 ANDL $0x00000001, CX
275 DECL CX
276 ORL $0xbfeffdfa, CX
277 ANDL CX, AX
278
279 // if (mask & (DV_I_44_0_bit | DV_I_48_0_bit | DV_II_47_0_bit | DV_II_54_0_bit | DV_II_56_0_bit)) != 0 {
280 // mask &= (((((W[38] >> 4) ^ (W[41] >> 29)) & 1) - 1) | ^(DV_I_44_0_bit | DV_I_48_0_bit | DV_II_47_0_bit | DV_II_54_0_bit | DV_II_56_0_bit))
281 // }
282 TESTL $0xa0080082, AX
283 JE f1
284 MOVL W_38+152(FP), CX
285 MOVL W_41+164(FP), DX
286 SHRL $0x04, CX
287 SHRL $0x1d, DX
288 XORL DX, CX
289 ANDL $0x00000001, CX
290 DECL CX
291 ORL $0x5ff7ff7d, CX
292 ANDL CX, AX
293
294f1:
295 // mask &= (((((W[37] >> 4) ^ (W[40] >> 29)) & 1) - 1) | ^(DV_I_43_0_bit | DV_I_47_0_bit | DV_II_46_0_bit | DV_II_53_0_bit | DV_II_55_0_bit))
296 MOVL W_37+148(FP), CX
297 MOVL W_40+160(FP), DX
298 SHRL $0x04, CX
299 SHRL $0x1d, DX
300 XORL DX, CX
301 ANDL $0x00000001, CX
302 DECL CX
303 ORL $0xaffdffde, CX
304 ANDL CX, AX
305
306 // if (mask & (DV_I_52_0_bit | DV_II_48_0_bit | DV_II_51_0_bit | DV_II_56_0_bit)) != 0 {
307 // mask &= (((((W[55] ^ W[56]) >> 29) & 1) - 1) | ^(DV_I_52_0_bit | DV_II_48_0_bit | DV_II_51_0_bit | DV_II_56_0_bit))
308 // }
309 TESTL $0x82108000, AX
310 JE f2
311 MOVL W_55+220(FP), CX
312 MOVL W_56+224(FP), DX
313 XORL DX, CX
314 SHRL $0x1d, CX
315 ANDL $0x00000001, CX
316 DECL CX
317 ORL $0x7def7fff, CX
318 ANDL CX, AX
319
320f2:
321 // if (mask & (DV_I_52_0_bit | DV_II_48_0_bit | DV_II_50_0_bit | DV_II_56_0_bit)) != 0 {
322 // mask &= ((((W[52] ^ (W[55] >> 25)) & (1 << 4)) - (1 << 4)) | ^(DV_I_52_0_bit | DV_II_48_0_bit | DV_II_50_0_bit | DV_II_56_0_bit))
323 // }
324 TESTL $0x80908000, AX
325 JE f3
326 MOVL W_52+208(FP), CX
327 MOVL W_55+220(FP), DX
328 SHRL $0x19, DX
329 XORL DX, CX
330 ANDL $0x00000010, CX
331 SUBL $0x00000010, CX
332 ORL $0x7f6f7fff, CX
333 ANDL CX, AX
334
335f3:
336 // if (mask & (DV_I_51_0_bit | DV_II_47_0_bit | DV_II_49_0_bit | DV_II_55_0_bit)) != 0 {
337 // mask &= ((((W[51] ^ (W[54] >> 25)) & (1 << 4)) - (1 << 4)) | ^(DV_I_51_0_bit | DV_II_47_0_bit | DV_II_49_0_bit | DV_II_55_0_bit))
338 // }
339 TESTL $0x40282000, AX
340 JE f4
341 MOVL W_51+204(FP), CX
342 MOVL W_54+216(FP), DX
343 SHRL $0x19, DX
344 XORL DX, CX
345 ANDL $0x00000010, CX
346 SUBL $0x00000010, CX
347 ORL $0xbfd7dfff, CX
348 ANDL CX, AX
349
350f4:
351 // if (mask & (DV_I_48_0_bit | DV_II_47_0_bit | DV_II_52_0_bit | DV_II_53_0_bit)) != 0 {
352 // mask &= (((((W[51] ^ W[52]) >> 29) & 1) - 1) | ^(DV_I_48_0_bit | DV_II_47_0_bit | DV_II_52_0_bit | DV_II_53_0_bit))
353 // }
354 TESTL $0x18080080, AX
355 JE f5
356 MOVL W_51+204(FP), CX
357 MOVL W_52+208(FP), DX
358 XORL DX, CX
359 SHRL $0x1d, CX
360 ANDL $0x00000001, CX
361 DECL CX
362 ORL $0xe7f7ff7f, CX
363 ANDL CX, AX
364
365f5:
366 // if (mask & (DV_I_46_0_bit | DV_I_49_0_bit | DV_II_45_0_bit | DV_II_48_0_bit)) != 0 {
367 // mask &= (((((W[36] >> 4) ^ (W[40] >> 29)) & 1) - 1) | ^(DV_I_46_0_bit | DV_I_49_0_bit | DV_II_45_0_bit | DV_II_48_0_bit))
368 // }
369 TESTL $0x00110208, AX
370 JE f6
371 MOVL W_36+144(FP), CX
372 SHRL $0x04, CX
373 MOVL W_40+160(FP), DX
374 SHRL $0x1d, DX
375 XORL DX, CX
376 ANDL $0x00000001, CX
377 DECL CX
378 ORL $0xffeefdf7, CX
379 ANDL CX, AX
380
381f6:
382 // if (mask & (DV_I_52_0_bit | DV_II_48_0_bit | DV_II_49_0_bit)) != 0 {
383 // mask &= ((0 - (((W[53] ^ W[56]) >> 29) & 1)) | ^(DV_I_52_0_bit | DV_II_48_0_bit | DV_II_49_0_bit))
384 // }
385 TESTL $0x00308000, AX
386 JE f7
387 MOVL W_53+212(FP), CX
388 MOVL W_56+224(FP), DX
389 XORL DX, CX
390 SHRL $0x1d, CX
391 ANDL $0x00000001, CX
392 NEGL CX
393 ORL $0xffcf7fff, CX
394 ANDL CX, AX
395
396f7:
397 // if (mask & (DV_I_50_0_bit | DV_II_46_0_bit | DV_II_47_0_bit)) != 0 {
398 // mask &= ((0 - (((W[51] ^ W[54]) >> 29) & 1)) | ^(DV_I_50_0_bit | DV_II_46_0_bit | DV_II_47_0_bit))
399 // }
400 TESTL $0x000a0800, AX
401 JE f8
402 MOVL W_51+204(FP), CX
403 MOVL W_54+216(FP), DX
404 XORL DX, CX
405 SHRL $0x1d, CX
406 ANDL $0x00000001, CX
407 NEGL CX
408 ORL $0xfff5f7ff, CX
409 ANDL CX, AX
410
411f8:
412 // if (mask & (DV_I_49_0_bit | DV_I_51_0_bit | DV_II_45_0_bit)) != 0 {
413 // mask &= ((0 - (((W[50] ^ W[52]) >> 29) & 1)) | ^(DV_I_49_0_bit | DV_I_51_0_bit | DV_II_45_0_bit))
414 // }
415 TESTL $0x00012200, AX
416 JE f9
417 MOVL W_50+200(FP), CX
418 MOVL W_52+208(FP), DX
419 XORL DX, CX
420 SHRL $0x1d, CX
421 ANDL $0x00000001, CX
422 NEGL CX
423 ORL $0xfffeddff, CX
424 ANDL CX, AX
425
426f9:
427 // if (mask & (DV_I_48_0_bit | DV_I_50_0_bit | DV_I_52_0_bit)) != 0 {
428 // mask &= ((0 - (((W[49] ^ W[51]) >> 29) & 1)) | ^(DV_I_48_0_bit | DV_I_50_0_bit | DV_I_52_0_bit))
429 // }
430 TESTL $0x00008880, AX
431 JE f10
432 MOVL W_49+196(FP), CX
433 MOVL W_51+204(FP), DX
434 XORL DX, CX
435 SHRL $0x1d, CX
436 ANDL $0x00000001, CX
437 NEGL CX
438 ORL $0xffff777f, CX
439 ANDL CX, AX
440
441f10:
442 // if (mask & (DV_I_47_0_bit | DV_I_49_0_bit | DV_I_51_0_bit)) != 0 {
443 // mask &= ((0 - (((W[48] ^ W[50]) >> 29) & 1)) | ^(DV_I_47_0_bit | DV_I_49_0_bit | DV_I_51_0_bit))
444 // }
445 TESTL $0x00002220, AX
446 JE f11
447 MOVL W_48+192(FP), CX
448 MOVL W_50+200(FP), DX
449 XORL DX, CX
450 SHRL $0x1d, CX
451 ANDL $0x00000001, CX
452 NEGL CX
453 ORL $0xffffdddf, CX
454 ANDL CX, AX
455
456f11:
457 // if (mask & (DV_I_46_0_bit | DV_I_48_0_bit | DV_I_50_0_bit)) != 0 {
458 // mask &= ((0 - (((W[47] ^ W[49]) >> 29) & 1)) | ^(DV_I_46_0_bit | DV_I_48_0_bit | DV_I_50_0_bit))
459 // }
460 TESTL $0x00000888, AX
461 JE f12
462 MOVL W_47+188(FP), CX
463 MOVL W_49+196(FP), DX
464 XORL DX, CX
465 SHRL $0x1d, CX
466 ANDL $0x00000001, CX
467 NEGL CX
468 ORL $0xfffff777, CX
469 ANDL CX, AX
470
471f12:
472 // if (mask & (DV_I_45_0_bit | DV_I_47_0_bit | DV_I_49_0_bit)) != 0 {
473 // mask &= ((0 - (((W[46] ^ W[48]) >> 29) & 1)) | ^(DV_I_45_0_bit | DV_I_47_0_bit | DV_I_49_0_bit))
474 // }
475 TESTL $0x00000224, AX
476 JE f13
477 MOVL W_46+184(FP), CX
478 MOVL W_48+192(FP), DX
479 XORL DX, CX
480 SHRL $0x1d, CX
481 ANDL $0x00000001, CX
482 NEGL CX
483 ORL $0xfffffddb, CX
484 ANDL CX, AX
485
486f13:
487 // mask &= ((((W[45] ^ W[47]) & (1 << 6)) - (1 << 6)) | ^(DV_I_47_2_bit | DV_I_49_2_bit | DV_I_51_2_bit))
488 MOVL W_45+180(FP), CX
489 MOVL W_47+188(FP), DX
490 XORL DX, CX
491 ANDL $0x00000040, CX
492 SUBL $0x00000040, CX
493 ORL $0xffffbbbf, CX
494 ANDL CX, AX
495
496 // if (mask & (DV_I_44_0_bit | DV_I_46_0_bit | DV_I_48_0_bit)) != 0 {
497 // mask &= ((0 - (((W[45] ^ W[47]) >> 29) & 1)) | ^(DV_I_44_0_bit | DV_I_46_0_bit | DV_I_48_0_bit))
498 // }
499 TESTL $0x0000008a, AX
500 JE f14
501 MOVL W_45+180(FP), CX
502 MOVL W_47+188(FP), DX
503 XORL DX, CX
504 SHRL $0x1d, CX
505 ANDL $0x00000001, CX
506 NEGL CX
507 ORL $0xffffff75, CX
508 ANDL CX, AX
509
510f14:
511 // mask &= (((((W[44] ^ W[46]) >> 6) & 1) - 1) | ^(DV_I_46_2_bit | DV_I_48_2_bit | DV_I_50_2_bit))
512 MOVL W_44+176(FP), CX
513 MOVL W_46+184(FP), DX
514 XORL DX, CX
515 SHRL $0x06, CX
516 ANDL $0x00000001, CX
517 DECL CX
518 ORL $0xffffeeef, CX
519 ANDL CX, AX
520
521 // if (mask & (DV_I_43_0_bit | DV_I_45_0_bit | DV_I_47_0_bit)) != 0 {
522 // mask &= ((0 - (((W[44] ^ W[46]) >> 29) & 1)) | ^(DV_I_43_0_bit | DV_I_45_0_bit | DV_I_47_0_bit))
523 // }
524 TESTL $0x00000025, AX
525 JE f15
526 MOVL W_44+176(FP), CX
527 MOVL W_46+184(FP), DX
528 XORL DX, CX
529 SHRL $0x1d, CX
530 ANDL $0x00000001, CX
531 NEGL CX
532 ORL $0xffffffda, CX
533 ANDL CX, AX
534
535f15:
536 // mask &= ((0 - ((W[41] ^ (W[42] >> 5)) & (1 << 1))) | ^(DV_I_48_2_bit | DV_II_46_2_bit | DV_II_51_2_bit))
537 MOVL W_41+164(FP), CX
538 MOVL W_42+168(FP), DX
539 SHRL $0x05, DX
540 XORL DX, CX
541 ANDL $0x00000002, CX
542 NEGL CX
543 ORL $0xfbfbfeff, CX
544 ANDL CX, AX
545
546 // mask &= ((0 - ((W[40] ^ (W[41] >> 5)) & (1 << 1))) | ^(DV_I_47_2_bit | DV_I_51_2_bit | DV_II_50_2_bit))
547 MOVL W_40+160(FP), CX
548 MOVL W_41+164(FP), DX
549 SHRL $0x05, DX
550 XORL DX, CX
551 ANDL $0x00000002, CX
552 NEGL CX
553 ORL $0xfeffbfbf, CX
554 ANDL CX, AX
555
556 // if (mask & (DV_I_44_0_bit | DV_I_46_0_bit | DV_II_56_0_bit)) != 0 {
557 // mask &= ((0 - (((W[40] ^ W[42]) >> 4) & 1)) | ^(DV_I_44_0_bit | DV_I_46_0_bit | DV_II_56_0_bit))
558 // }
559 TESTL $0x8000000a, AX
560 JE f16
561 MOVL W_40+160(FP), CX
562 MOVL W_42+168(FP), DX
563 XORL DX, CX
564 SHRL $0x04, CX
565 ANDL $0x00000001, CX
566 NEGL CX
567 ORL $0x7ffffff5, CX
568 ANDL CX, AX
569
570f16:
571 // mask &= ((0 - ((W[39] ^ (W[40] >> 5)) & (1 << 1))) | ^(DV_I_46_2_bit | DV_I_50_2_bit | DV_II_49_2_bit))
572 MOVL W_39+156(FP), CX
573 MOVL W_40+160(FP), DX
574 SHRL $0x05, DX
575 XORL DX, CX
576 ANDL $0x00000002, CX
577 NEGL CX
578 ORL $0xffbfefef, CX
579 ANDL CX, AX
580
581 // if (mask & (DV_I_43_0_bit | DV_I_45_0_bit | DV_II_55_0_bit)) != 0 {
582 // mask &= ((0 - (((W[39] ^ W[41]) >> 4) & 1)) | ^(DV_I_43_0_bit | DV_I_45_0_bit | DV_II_55_0_bit))
583 // }
584 TESTL $0x40000005, AX
585 JE f17
586 MOVL W_39+156(FP), CX
587 MOVL W_41+164(FP), DX
588 XORL DX, CX
589 SHRL $0x04, CX
590 ANDL $0x00000001, CX
591 NEGL CX
592 ORL $0xbffffffa, CX
593 ANDL CX, AX
594
595f17:
596 // if (mask & (DV_I_44_0_bit | DV_II_54_0_bit | DV_II_56_0_bit)) != 0 {
597 // mask &= ((0 - (((W[38] ^ W[40]) >> 4) & 1)) | ^(DV_I_44_0_bit | DV_II_54_0_bit | DV_II_56_0_bit))
598 // }
599 TESTL $0xa0000002, AX
600 JE f18
601 MOVL W_38+152(FP), CX
602 MOVL W_40+160(FP), DX
603 XORL DX, CX
604 SHRL $0x04, CX
605 ANDL $0x00000001, CX
606 NEGL CX
607 ORL $0x5ffffffd, CX
608 ANDL CX, AX
609
610f18:
611 // if (mask & (DV_I_43_0_bit | DV_II_53_0_bit | DV_II_55_0_bit)) != 0 {
612 // mask &= ((0 - (((W[37] ^ W[39]) >> 4) & 1)) | ^(DV_I_43_0_bit | DV_II_53_0_bit | DV_II_55_0_bit))
613 // }
614 TESTL $0x50000001, AX
615 JE f19
616 MOVL W_37+148(FP), CX
617 MOVL W_39+156(FP), DX
618 XORL DX, CX
619 SHRL $0x04, CX
620 ANDL $0x00000001, CX
621 NEGL CX
622 ORL $0xaffffffe, CX
623 ANDL CX, AX
624
625f19:
626 // mask &= ((0 - ((W[36] ^ (W[37] >> 5)) & (1 << 1))) | ^(DV_I_47_2_bit | DV_I_50_2_bit | DV_II_46_2_bit))
627 MOVL W_36+144(FP), CX
628 MOVL W_37+148(FP), DX
629 SHRL $0x05, DX
630 XORL DX, CX
631 ANDL $0x00000002, CX
632 NEGL CX
633 ORL $0xfffbefbf, CX
634 ANDL CX, AX
635
636 // if (mask & (DV_I_45_0_bit | DV_I_48_0_bit | DV_II_47_0_bit)) != 0 {
637 // mask &= (((((W[35] >> 4) ^ (W[39] >> 29)) & 1) - 1) | ^(DV_I_45_0_bit | DV_I_48_0_bit | DV_II_47_0_bit))
638 // }
639 TESTL $0x00080084, AX
640 JE f20
641 MOVL W_35+140(FP), CX
642 MOVL W_39+156(FP), DX
643 SHRL $0x04, CX
644 SHRL $0x1d, DX
645 XORL DX, CX
646 ANDL $0x00000001, CX
647 SUBL $0x00000001, CX
648 ORL $0xfff7ff7b, CX
649 ANDL CX, AX
650
651f20:
652 // if (mask & (DV_I_48_0_bit | DV_II_48_0_bit)) != 0 {
653 // mask &= ((0 - ((W[63] ^ (W[64] >> 5)) & (1 << 0))) | ^(DV_I_48_0_bit | DV_II_48_0_bit))
654 // }
655 TESTL $0x00100080, AX
656 JE f21
657 MOVL W_63+252(FP), CX
658 MOVL W_64+256(FP), DX
659 SHRL $0x05, DX
660 XORL DX, CX
661 ANDL $0x00000001, CX
662 NEGL CX
663 ORL $0xffefff7f, CX
664 ANDL CX, AX
665
666f21:
667 // if (mask & (DV_I_45_0_bit | DV_II_45_0_bit)) != 0 {
668 // mask &= ((0 - ((W[63] ^ (W[64] >> 5)) & (1 << 1))) | ^(DV_I_45_0_bit | DV_II_45_0_bit))
669 // }
670 TESTL $0x00010004, AX
671 JE f22
672 MOVL W_63+252(FP), CX
673 MOVL W_64+256(FP), DX
674 SHRL $0x05, DX
675 XORL DX, CX
676 ANDL $0x00000002, CX
677 NEGL CX
678 ORL $0xfffefffb, CX
679 ANDL CX, AX
680
681f22:
682 // if (mask & (DV_I_47_0_bit | DV_II_47_0_bit)) != 0 {
683 // mask &= ((0 - ((W[62] ^ (W[63] >> 5)) & (1 << 0))) | ^(DV_I_47_0_bit | DV_II_47_0_bit))
684 // }
685 TESTL $0x00080020, AX
686 JE f23
687 MOVL W_62+248(FP), CX
688 MOVL W_63+252(FP), DX
689 SHRL $0x05, DX
690 XORL DX, CX
691 ANDL $0x00000001, CX
692 NEGL CX
693 ORL $0xfff7ffdf, CX
694 ANDL CX, AX
695
696f23:
697 // if (mask & (DV_I_46_0_bit | DV_II_46_0_bit)) != 0 {
698 // mask &= ((0 - ((W[61] ^ (W[62] >> 5)) & (1 << 0))) | ^(DV_I_46_0_bit | DV_II_46_0_bit))
699 // }
700 TESTL $0x00020008, AX
701 JE f24
702 MOVL W_61+244(FP), CX
703 MOVL W_62+248(FP), DX
704 SHRL $0x05, DX
705 XORL DX, CX
706 ANDL $0x00000001, CX
707 NEGL CX
708 ORL $0xfffdfff7, CX
709 ANDL CX, AX
710
711f24:
712 // mask &= ((0 - ((W[61] ^ (W[62] >> 5)) & (1 << 2))) | ^(DV_I_46_2_bit | DV_II_46_2_bit))
713 MOVL W_61+244(FP), CX
714 MOVL W_62+248(FP), DX
715 SHRL $0x05, DX
716 XORL DX, CX
717 ANDL $0x00000004, CX
718 NEGL CX
719 ORL $0xfffbffef, CX
720 ANDL CX, AX
721
722 // if (mask & (DV_I_45_0_bit | DV_II_45_0_bit)) != 0 {
723 // mask &= ((0 - ((W[60] ^ (W[61] >> 5)) & (1 << 0))) | ^(DV_I_45_0_bit | DV_II_45_0_bit))
724 // }
725 TESTL $0x00010004, AX
726 JE f25
727 MOVL W_60+240(FP), CX
728 MOVL W_61+244(FP), DX
729 SHRL $0x05, DX
730 XORL DX, CX
731 ANDL $0x00000001, CX
732 NEGL CX
733 ORL $0xfffefffb, CX
734 ANDL CX, AX
735
736f25:
737 // if (mask & (DV_II_51_0_bit | DV_II_54_0_bit)) != 0 {
738 // mask &= (((((W[58] ^ W[59]) >> 29) & 1) - 1) | ^(DV_II_51_0_bit | DV_II_54_0_bit))
739 // }
740 TESTL $0x22000000, AX
741 JE f26
742 MOVL W_58+232(FP), CX
743 MOVL W_59+236(FP), DX
744 XORL DX, CX
745 SHRL $0x1d, CX
746 ANDL $0x00000001, CX
747 SUBL $0x00000001, CX
748 ORL $0xddffffff, CX
749 ANDL CX, AX
750
751f26:
752 // if (mask & (DV_II_50_0_bit | DV_II_53_0_bit)) != 0 {
753 // mask &= (((((W[57] ^ W[58]) >> 29) & 1) - 1) | ^(DV_II_50_0_bit | DV_II_53_0_bit))
754 // }
755 TESTL $0x10800000, AX
756 JE f27
757 MOVL W_57+228(FP), CX
758 MOVL W_58+232(FP), DX
759 XORL DX, CX
760 SHRL $0x1d, CX
761 ANDL $0x00000001, CX
762 SUBL $0x00000001, CX
763 ORL $0xef7fffff, CX
764 ANDL CX, AX
765
766f27:
767 // if (mask & (DV_II_52_0_bit | DV_II_54_0_bit)) != 0 {
768 // mask &= ((((W[56] ^ (W[59] >> 25)) & (1 << 4)) - (1 << 4)) | ^(DV_II_52_0_bit | DV_II_54_0_bit))
769 // }
770 TESTL $0x28000000, AX
771 JE f28
772 MOVL W_56+224(FP), CX
773 MOVL W_59+236(FP), DX
774 SHRL $0x19, DX
775 XORL DX, CX
776 ANDL $0x00000010, CX
777 SUBL $0x00000010, CX
778 ORL $0xd7ffffff, CX
779 ANDL CX, AX
780
781f28:
782 // if (mask & (DV_II_51_0_bit | DV_II_52_0_bit)) != 0 {
783 // mask &= ((0 - (((W[56] ^ W[59]) >> 29) & 1)) | ^(DV_II_51_0_bit | DV_II_52_0_bit))
784 // }
785 TESTL $0x0a000000, AX
786 JE f29
787 MOVL W_56+224(FP), CX
788 MOVL W_59+236(FP), DX
789 XORL DX, CX
790 SHRL $0x1d, CX
791 ANDL $0x00000001, CX
792 NEGL CX
793 ORL $0xf5ffffff, CX
794 ANDL CX, AX
795
796f29:
797 // if (mask & (DV_II_49_0_bit | DV_II_52_0_bit)) != 0 {
798 // mask &= (((((W[56] ^ W[57]) >> 29) & 1) - 1) | ^(DV_II_49_0_bit | DV_II_52_0_bit))
799 // }
800 TESTL $0x08200000, AX
801 JE f30
802 MOVL W_56+224(FP), CX
803 MOVL W_57+228(FP), DX
804 XORL DX, CX
805 SHRL $0x1d, CX
806 ANDL $0x00000001, CX
807 SUBL $0x00000001, CX
808 ORL $0xf7dfffff, CX
809 ANDL CX, AX
810
811f30:
812 // if (mask & (DV_II_51_0_bit | DV_II_53_0_bit)) != 0 {
813 // mask &= ((((W[55] ^ (W[58] >> 25)) & (1 << 4)) - (1 << 4)) | ^(DV_II_51_0_bit | DV_II_53_0_bit))
814 // }
815 TESTL $0x12000000, AX
816 JE f31
817 MOVL W_55+220(FP), CX
818 MOVL W_58+232(FP), DX
819 SHRL $0x19, DX
820 XORL DX, CX
821 ANDL $0x00000010, CX
822 SUBL $0x00000010, CX
823 ORL $0xedffffff, CX
824 ANDL CX, AX
825
826f31:
827 // if (mask & (DV_II_50_0_bit | DV_II_52_0_bit)) != 0 {
828 // mask &= ((((W[54] ^ (W[57] >> 25)) & (1 << 4)) - (1 << 4)) | ^(DV_II_50_0_bit | DV_II_52_0_bit))
829 // }
830 TESTL $0x08800000, AX
831 JE f32
832 MOVL W_54+216(FP), CX
833 MOVL W_57+228(FP), DX
834 SHRL $0x19, DX
835 XORL DX, CX
836 ANDL $0x00000010, CX
837 SUBL $0x00000010, CX
838 ORL $0xf77fffff, CX
839 ANDL CX, AX
840
841f32:
842 // if (mask & (DV_II_49_0_bit | DV_II_51_0_bit)) != 0 {
843 // mask &= ((((W[53] ^ (W[56] >> 25)) & (1 << 4)) - (1 << 4)) | ^(DV_II_49_0_bit | DV_II_51_0_bit))
844 // }
845 TESTL $0x02200000, AX
846 JE f33
847 MOVL W_53+212(FP), CX
848 MOVL W_56+224(FP), DX
849 SHRL $0x19, DX
850 XORL DX, CX
851 ANDL $0x00000010, CX
852 SUBL $0x00000010, CX
853 ORL $0xfddfffff, CX
854 ANDL CX, AX
855
856f33:
857 // mask &= ((((W[51] ^ (W[50] >> 5)) & (1 << 1)) - (1 << 1)) | ^(DV_I_50_2_bit | DV_II_46_2_bit))
858 MOVL W_51+204(FP), CX
859 MOVL W_50+200(FP), DX
860 SHRL $0x05, DX
861 XORL DX, CX
862 ANDL $0x00000002, CX
863 SUBL $0x00000002, CX
864 ORL $0xfffbefff, CX
865 ANDL CX, AX
866
867 // mask &= ((((W[48] ^ W[50]) & (1 << 6)) - (1 << 6)) | ^(DV_I_50_2_bit | DV_II_46_2_bit))
868 MOVL W_48+192(FP), CX
869 MOVL W_50+200(FP), DX
870 XORL DX, CX
871 ANDL $0x00000040, CX
872 SUBL $0x00000040, CX
873 ORL $0xfffbefff, CX
874 ANDL CX, AX
875
876 // if (mask & (DV_I_51_0_bit | DV_I_52_0_bit)) != 0 {
877 // mask &= ((0 - (((W[48] ^ W[55]) >> 29) & 1)) | ^(DV_I_51_0_bit | DV_I_52_0_bit))
878 // }
879 TESTL $0x0000a000, AX
880 JE f34
881 MOVL W_48+192(FP), CX
882 MOVL W_55+220(FP), DX
883 XORL DX, CX
884 SHRL $0x1d, CX
885 ANDL $0x00000001, CX
886 NEGL CX
887 ORL $0xffff5fff, CX
888 ANDL CX, AX
889
890f34:
891 // mask &= ((((W[47] ^ W[49]) & (1 << 6)) - (1 << 6)) | ^(DV_I_49_2_bit | DV_I_51_2_bit))
892 MOVL W_47+188(FP), CX
893 MOVL W_49+196(FP), DX
894 XORL DX, CX
895 ANDL $0x00000040, CX
896 SUBL $0x00000040, CX
897 ORL $0xffffbbff, CX
898 ANDL CX, AX
899
900 // mask &= ((((W[48] ^ (W[47] >> 5)) & (1 << 1)) - (1 << 1)) | ^(DV_I_47_2_bit | DV_II_51_2_bit))
901 MOVL W_48+192(FP), CX
902 MOVL W_47+188(FP), DX
903 SHRL $0x05, DX
904 XORL DX, CX
905 ANDL $0x00000002, CX
906 SUBL $0x00000002, CX
907 ORL $0xfbffffbf, CX
908 ANDL CX, AX
909
910 // mask &= ((((W[46] ^ W[48]) & (1 << 6)) - (1 << 6)) | ^(DV_I_48_2_bit | DV_I_50_2_bit))
911 MOVL W_46+184(FP), CX
912 MOVL W_48+192(FP), DX
913 XORL DX, CX
914 ANDL $0x00000040, CX
915 SUBL $0x00000040, CX
916 ORL $0xffffeeff, CX
917 ANDL CX, AX
918
919 // mask &= ((((W[47] ^ (W[46] >> 5)) & (1 << 1)) - (1 << 1)) | ^(DV_I_46_2_bit | DV_II_50_2_bit))
920 MOVL W_47+188(FP), CX
921 MOVL W_46+184(FP), DX
922 SHRL $0x05, DX
923 XORL DX, CX
924 ANDL $0x00000002, CX
925 SUBL $0x00000002, CX
926 ORL $0xfeffffef, CX
927 ANDL CX, AX
928
929 // mask &= ((0 - ((W[44] ^ (W[45] >> 5)) & (1 << 1))) | ^(DV_I_51_2_bit | DV_II_49_2_bit))
930 MOVL W_44+176(FP), CX
931 MOVL W_45+180(FP), DX
932 SHRL $0x05, DX
933 XORL DX, CX
934 ANDL $0x00000002, CX
935 NEGL CX
936 ORL $0xffbfbfff, CX
937 ANDL CX, AX
938
939 // mask &= ((((W[43] ^ W[45]) & (1 << 6)) - (1 << 6)) | ^(DV_I_47_2_bit | DV_I_49_2_bit))
940 MOVL W_43+172(FP), CX
941 MOVL W_45+180(FP), DX
942 XORL DX, CX
943 ANDL $0x00000040, CX
944 SUBL $0x00000040, CX
945 ORL $0xfffffbbf, CX
946 ANDL CX, AX
947
948 // mask &= (((((W[42] ^ W[44]) >> 6) & 1) - 1) | ^(DV_I_46_2_bit | DV_I_48_2_bit))
949 MOVL W_42+168(FP), CX
950 MOVL W_44+176(FP), DX
951 XORL DX, CX
952 SHRL $0x06, CX
953 ANDL $0x00000001, CX
954 SUBL $0x00000001, CX
955 ORL $0xfffffeef, CX
956 ANDL CX, AX
957
958 // mask &= ((((W[43] ^ (W[42] >> 5)) & (1 << 1)) - (1 << 1)) | ^(DV_II_46_2_bit | DV_II_51_2_bit))
959 MOVL W_43+172(FP), CX
960 MOVL W_42+168(FP), DX
961 SHRL $0x05, DX
962 XORL DX, CX
963 ANDL $0x00000002, CX
964 SUBL $0x00000002, CX
965 ORL $0xfbfbffff, CX
966 ANDL CX, AX
967
968 // mask &= ((((W[42] ^ (W[41] >> 5)) & (1 << 1)) - (1 << 1)) | ^(DV_I_51_2_bit | DV_II_50_2_bit))
969 MOVL W_42+168(FP), CX
970 MOVL W_41+164(FP), DX
971 SHRL $0x05, DX
972 XORL DX, CX
973 ANDL $0x00000002, CX
974 SUBL $0x00000002, CX
975 ORL $0xfeffbfff, CX
976 ANDL CX, AX
977
978 // mask &= ((((W[41] ^ (W[40] >> 5)) & (1 << 1)) - (1 << 1)) | ^(DV_I_50_2_bit | DV_II_49_2_bit))
979 MOVL W_41+164(FP), CX
980 MOVL W_40+160(FP), DX
981 SHRL $0x05, DX
982 XORL DX, CX
983 ANDL $0x00000002, CX
984 SUBL $0x00000002, CX
985 ORL $0xffbfefff, CX
986 ANDL CX, AX
987
988 // if (mask & (DV_I_52_0_bit | DV_II_51_0_bit)) != 0 {
989 // mask &= ((((W[39] ^ (W[43] >> 25)) & (1 << 4)) - (1 << 4)) | ^(DV_I_52_0_bit | DV_II_51_0_bit))
990 // }
991 TESTL $0x02008000, AX
992 JE f35
993 MOVL W_39+156(FP), CX
994 MOVL W_43+172(FP), DX
995 SHRL $0x19, DX
996 XORL DX, CX
997 ANDL $0x00000010, CX
998 SUBL $0x00000010, CX
999 ORL $0xfdff7fff, CX
1000 ANDL CX, AX
1001
1002f35:
1003 // if (mask & (DV_I_51_0_bit | DV_II_50_0_bit)) != 0 {
1004 // mask &= ((((W[38] ^ (W[42] >> 25)) & (1 << 4)) - (1 << 4)) | ^(DV_I_51_0_bit | DV_II_50_0_bit))
1005 // }
1006 TESTL $0x00802000, AX
1007 JE f36
1008 MOVL W_38+152(FP), CX
1009 MOVL W_42+168(FP), DX
1010 SHRL $0x19, DX
1011 XORL DX, CX
1012 ANDL $0x00000010, CX
1013 SUBL $0x00000010, CX
1014 ORL $0xff7fdfff, CX
1015 ANDL CX, AX
1016
1017f36:
1018 // if (mask & (DV_I_48_2_bit | DV_I_51_2_bit)) != 0 {
1019 // mask &= ((0 - ((W[37] ^ (W[38] >> 5)) & (1 << 1))) | ^(DV_I_48_2_bit | DV_I_51_2_bit))
1020 // }
1021 TESTL $0x00004100, AX
1022 JE f37
1023 MOVL W_37+148(FP), CX
1024 MOVL W_38+152(FP), DX
1025 SHRL $0x05, DX
1026 XORL DX, CX
1027 ANDL $0x00000002, CX
1028 NEGL CX
1029 ORL $0xffffbeff, CX
1030 ANDL CX, AX
1031
1032f37:
1033 // if (mask & (DV_I_50_0_bit | DV_II_49_0_bit)) != 0 {
1034 // mask &= ((((W[37] ^ (W[41] >> 25)) & (1 << 4)) - (1 << 4)) | ^(DV_I_50_0_bit | DV_II_49_0_bit))
1035 // }
1036 TESTL $0x00200800, AX
1037 JE f38
1038 MOVL W_37+148(FP), CX
1039 MOVL W_41+164(FP), DX
1040 SHRL $0x19, DX
1041 XORL DX, CX
1042 ANDL $0x00000010, CX
1043 SUBL $0x00000010, CX
1044 ORL $0xffdff7ff, CX
1045 ANDL CX, AX
1046
1047f38:
1048 // if (mask & (DV_II_52_0_bit | DV_II_54_0_bit)) != 0 {
1049 // mask &= ((0 - ((W[36] ^ W[38]) & (1 << 4))) | ^(DV_II_52_0_bit | DV_II_54_0_bit))
1050 // }
1051 TESTL $0x28000000, AX
1052 JE f39
1053 MOVL W_36+144(FP), CX
1054 MOVL W_38+152(FP), DX
1055 XORL DX, CX
1056 ANDL $0x00000010, CX
1057 NEGL CX
1058 ORL $0xd7ffffff, CX
1059 ANDL CX, AX
1060
1061f39:
1062 // mask &= ((0 - ((W[35] ^ (W[36] >> 5)) & (1 << 1))) | ^(DV_I_46_2_bit | DV_I_49_2_bit))
1063 MOVL W_35+140(FP), CX
1064 MOVL W_36+144(FP), DX
1065 SHRL $0x05, DX
1066 XORL DX, CX
1067 ANDL $0x00000002, CX
1068 NEGL CX
1069 ORL $0xfffffbef, CX
1070 ANDL CX, AX
1071
1072 // if (mask & (DV_I_51_0_bit | DV_II_47_0_bit)) != 0 {
1073 // mask &= ((((W[35] ^ (W[39] >> 25)) & (1 << 3)) - (1 << 3)) | ^(DV_I_51_0_bit | DV_II_47_0_bit))
1074 // }
1075 TESTL $0x00082000, AX
1076 JE f40
1077 MOVL W_35+140(FP), CX
1078 MOVL W_39+156(FP), DX
1079 SHRL $0x19, DX
1080 XORL DX, CX
1081 ANDL $0x00000008, CX
1082 SUBL $0x00000008, CX
1083 ORL $0xfff7dfff, CX
1084 ANDL CX, AX
1085
1086f40:
1087 // if mask != 0
1088 TESTL $0x00000000, AX
1089 JNE end
1090
1091 // if (mask & DV_I_43_0_bit) != 0 {
1092 // if not((W[61]^(W[62]>>5))&(1<<1)) != 0 ||
1093 // not(not((W[59]^(W[63]>>25))&(1<<5))) != 0 ||
1094 // not((W[58]^(W[63]>>30))&(1<<0)) != 0 {
1095 // mask &= ^DV_I_43_0_bit
1096 // }
1097 // }
1098 BTL $0x00, AX
1099 JNC f41_skip
1100 MOVL W_61+244(FP), CX
1101 MOVL W_62+248(FP), DX
1102 SHRL $0x05, DX
1103 XORL DX, CX
1104 ANDL $0x00000002, CX
1105 NEGL CX
1106 CMPL CX, $0x00000000
1107 JE f41_in
1108 MOVL W_59+236(FP), CX
1109 MOVL W_63+252(FP), DX
1110 SHRL $0x19, DX
1111 XORL DX, CX
1112 ANDL $0x00000020, CX
1113 CMPL CX, $0x00000000
1114 JNE f41_in
1115 MOVL W_58+232(FP), CX
1116 MOVL W_63+252(FP), DX
1117 SHRL $0x1e, DX
1118 XORL DX, CX
1119 ANDL $0x00000001, CX
1120 NEGL CX
1121 CMPL CX, $0x00000000
1122 JE f41_in
1123 JMP f41_skip
1124
1125f41_in:
1126 ANDL $0xfffffffe, AX
1127
1128f41_skip:
1129 // if (mask & DV_I_44_0_bit) != 0 {
1130 // if not((W[62]^(W[63]>>5))&(1<<1)) != 0 ||
1131 // not(not((W[60]^(W[64]>>25))&(1<<5))) != 0 ||
1132 // not((W[59]^(W[64]>>30))&(1<<0)) != 0 {
1133 // mask &= ^DV_I_44_0_bit
1134 // }
1135 // }
1136 BTL $0x01, AX
1137 JNC f42_skip
1138 MOVL W_62+248(FP), CX
1139 MOVL W_63+252(FP), DX
1140 SHRL $0x05, DX
1141 XORL DX, CX
1142 ANDL $0x00000002, CX
1143 NEGL CX
1144 CMPL CX, $0x00000000
1145 JE f42_in
1146 MOVL W_60+240(FP), CX
1147 MOVL W_64+256(FP), DX
1148 SHRL $0x19, DX
1149 XORL DX, CX
1150 ANDL $0x00000020, CX
1151 CMPL CX, $0x00000000
1152 JNE f42_in
1153 MOVL W_59+236(FP), CX
1154 MOVL W_64+256(FP), DX
1155 SHRL $0x1e, DX
1156 XORL DX, CX
1157 ANDL $0x00000001, CX
1158 NEGL CX
1159 CMPL CX, $0x00000000
1160 JE f42_in
1161 JMP f42_skip
1162
1163f42_in:
1164 ANDL $0xfffffffd, AX
1165
1166f42_skip:
1167 // if (mask & DV_I_46_2_bit) != 0 {
1168 // mask &= ((^((W[40] ^ W[42]) >> 2)) | ^DV_I_46_2_bit)
1169 // }
1170 BTL $0x04, AX
1171 JNC f43
1172 MOVL W_40+160(FP), CX
1173 MOVL W_42+168(FP), DX
1174 XORL DX, CX
1175 SHRL $0x02, CX
1176 NOTL CX
1177 ORL $0xffffffef, CX
1178 ANDL CX, AX
1179
1180f43:
1181 // if (mask & DV_I_47_2_bit) != 0 {
1182 // if not((W[62]^(W[63]>>5))&(1<<2)) != 0 ||
1183 // not(not((W[41]^W[43])&(1<<6))) != 0 {
1184 // mask &= ^DV_I_47_2_bit
1185 // }
1186 // }
1187 BTL $0x06, AX
1188 JNC f44_skip
1189 MOVL W_62+248(FP), CX
1190 MOVL W_63+252(FP), DX
1191 SHRL $0x05, DX
1192 XORL DX, CX
1193 ANDL $0x00000004, CX
1194 NEGL CX
1195 CMPL CX, $0x00000000
1196 JE f44_in
1197 MOVL W_41+164(FP), CX
1198 MOVL W_43+172(FP), DX
1199 XORL DX, CX
1200 ANDL $0x00000040, CX
1201 CMPL CX, $0x00000000
1202 JNE f44_in
1203 JMP f44_skip
1204
1205f44_in:
1206 ANDL $0xffffffbf, AX
1207
1208f44_skip:
1209 // if (mask & DV_I_48_2_bit) != 0 {
1210 // if not((W[63]^(W[64]>>5))&(1<<2)) != 0 ||
1211 // not(not((W[48]^(W[49]<<5))&(1<<6))) != 0 {
1212 // mask &= ^DV_I_48_2_bit
1213 // }
1214 // }
1215 BTL $0x08, AX
1216 JNC f45_skip
1217 MOVL W_63+252(FP), CX
1218 MOVL W_64+256(FP), DX
1219 SHRL $0x05, DX
1220 XORL DX, CX
1221 ANDL $0x00000004, CX
1222 NEGL CX
1223 CMPL CX, $0x00000000
1224 JE f45_in
1225 MOVL W_48+192(FP), CX
1226 MOVL W_49+196(FP), DX
1227 SHLL $0x05, DX
1228 XORL DX, CX
1229 ANDL $0x00000040, CX
1230 CMPL CX, $0x00000000
1231 JNE f45_in
1232 JMP f45_skip
1233
1234f45_in:
1235 ANDL $0xfffffeff, AX
1236
1237f45_skip:
1238 // if (mask & DV_I_49_2_bit) != 0 {
1239 // if not(not((W[49]^(W[50]<<5))&(1<<6))) != 0 ||
1240 // not((W[42]^W[50])&(1<<1)) != 0 ||
1241 // not(not((W[39]^(W[40]<<5))&(1<<6))) != 0 ||
1242 // not((W[38]^W[40])&(1<<1)) != 0 {
1243 // mask &= ^DV_I_49_2_bit
1244 // }
1245 // }
1246 BTL $0x0a, AX
1247 JNC f46_skip
1248 MOVL W_49+196(FP), CX
1249 MOVL W_50+200(FP), DX
1250 SHLL $0x05, DX
1251 XORL DX, CX
1252 ANDL $0x00000040, CX
1253 CMPL CX, $0x00000000
1254 JNE f46_in
1255 MOVL W_42+168(FP), CX
1256 MOVL W_50+200(FP), DX
1257 XORL DX, CX
1258 ANDL $0x00000002, CX
1259 CMPL CX, $0x00000000
1260 JE f46_in
1261 MOVL W_39+156(FP), CX
1262 MOVL W_40+160(FP), DX
1263 SHLL $0x05, DX
1264 XORL DX, CX
1265 ANDL $0x00000040, CX
1266 CMPL CX, $0x00000000
1267 JNE f46_in
1268 MOVL W_38+152(FP), CX
1269 MOVL W_40+160(FP), DX
1270 XORL DX, CX
1271 ANDL $0x00000002, CX
1272 CMPL CX, $0x00000000
1273 JE f46_in
1274 JMP f46_skip
1275
1276f46_in:
1277 ANDL $0xfffffbff, AX
1278
1279f46_skip:
1280 // if (mask & DV_I_50_0_bit) != 0 {
1281 // mask &= (((W[36] ^ W[37]) << 7) | ^DV_I_50_0_bit)
1282 // }
1283 BTL $0x0b, AX
1284 JNC f47
1285 MOVL W_36+144(FP), CX
1286 MOVL W_37+148(FP), DX
1287 XORL DX, CX
1288 SHLL $0x07, CX
1289 ORL $0xfffff7ff, CX
1290 ANDL CX, AX
1291
1292f47:
1293 // if (mask & DV_I_50_2_bit) != 0 {
1294 // mask &= (((W[43] ^ W[51]) << 11) | ^DV_I_50_2_bit)
1295 // }
1296 BTL $0x0c, AX
1297 JNC f48
1298 MOVL W_43+172(FP), CX
1299 MOVL W_51+204(FP), DX
1300 XORL DX, CX
1301 SHLL $0x0b, CX
1302 ORL $0xffffefff, CX
1303 ANDL CX, AX
1304
1305f48:
1306 // if (mask & DV_I_51_0_bit) != 0 {
1307 // mask &= (((W[37] ^ W[38]) << 9) | ^DV_I_51_0_bit)
1308 // }
1309 BTL $0x0d, AX
1310 JNC f49
1311 MOVL W_37+148(FP), CX
1312 MOVL W_38+152(FP), DX
1313 XORL DX, CX
1314 SHLL $0x09, CX
1315 ORL $0xffffdfff, CX
1316 ANDL CX, AX
1317
1318f49:
1319 // if (mask & DV_I_51_2_bit) != 0 {
1320 // if not(not((W[51]^(W[52]<<5))&(1<<6))) != 0 ||
1321 // not(not((W[49]^W[51])&(1<<6))) != 0 ||
1322 // not(not((W[37]^(W[37]>>5))&(1<<1))) != 0 ||
1323 // not(not((W[35]^(W[39]>>25))&(1<<5))) != 0 {
1324 // mask &= ^DV_I_51_2_bit
1325 // }
1326 // }
1327 BTL $0x0e, AX
1328 JNC f50_skip
1329 MOVL W_51+204(FP), CX
1330 MOVL W_52+208(FP), DX
1331 SHLL $0x05, DX
1332 XORL DX, CX
1333 ANDL $0x00000040, CX
1334 CMPL CX, $0x00000000
1335 JNE f50_in
1336 MOVL W_49+196(FP), CX
1337 MOVL W_51+204(FP), DX
1338 XORL DX, CX
1339 ANDL $0x00000040, CX
1340 CMPL CX, $0x00000000
1341 JNE f50_in
1342 MOVL W_37+148(FP), CX
1343 MOVL W_37+148(FP), DX
1344 SHRL $0x05, DX
1345 XORL DX, CX
1346 ANDL $0x00000002, CX
1347 CMPL CX, $0x00000000
1348 JNE f50_in
1349 MOVL W_35+140(FP), CX
1350 MOVL W_39+156(FP), DX
1351 SHRL $0x19, DX
1352 XORL DX, CX
1353 ANDL $0x00000020, CX
1354 CMPL CX, $0x00000000
1355 JNE f50_in
1356 JMP f50_skip
1357
1358f50_in:
1359 ANDL $0xffffbfff, AX
1360
1361f50_skip:
1362 // if (mask & DV_I_52_0_bit) != 0 {
1363 // mask &= (((W[38] ^ W[39]) << 11) | ^DV_I_52_0_bit)
1364 // }
1365 BTL $0x0f, AX
1366 JNC f51
1367 MOVL W_38+152(FP), CX
1368 MOVL W_39+156(FP), DX
1369 XORL DX, CX
1370 SHLL $0x0b, CX
1371 ORL $0xffff7fff, CX
1372 ANDL CX, AX
1373
1374f51:
1375 // if (mask & DV_II_46_2_bit) != 0 {
1376 // mask &= (((W[47] ^ W[51]) << 17) | ^DV_II_46_2_bit)
1377 // }
1378 TESTL $0x00040000, AX
1379 BTL $0x12, AX
1380 JNC f52
1381 MOVL W_47+188(FP), CX
1382 MOVL W_51+204(FP), DX
1383 XORL DX, CX
1384 SHLL $0x11, CX
1385 ORL $0xfffbffff, CX
1386 ANDL CX, AX
1387
1388f52:
1389 // if (mask & DV_II_48_0_bit) != 0 {
1390 // if not(not((W[36]^(W[40]>>25))&(1<<3))) != 0 ||
1391 // not((W[35]^(W[40]<<2))&(1<<30)) != 0 {
1392 // mask &= ^DV_II_48_0_bit
1393 // }
1394 // }
1395 BTL $0x14, AX
1396 JNC f53_skip
1397 MOVL W_36+144(FP), CX
1398 MOVL W_40+160(FP), DX
1399 SHRL $0x19, DX
1400 XORL DX, CX
1401 ANDL $0x00000008, CX
1402 CMPL CX, $0x00000000
1403 JNE f53_in
1404 MOVL W_35+140(FP), CX
1405 MOVL W_40+160(FP), DX
1406 SHLL $0x02, DX
1407 XORL DX, CX
1408 ANDL $0x40000000, CX
1409 CMPL CX, $0x00000000
1410 JNE f53_in
1411 JMP f53_skip
1412
1413f53_in:
1414 ANDL $0xffefffff, AX
1415
1416f53_skip:
1417 // if (mask & DV_II_49_0_bit) != 0 {
1418 // if not(not((W[37]^(W[41]>>25))&(1<<3))) != 0 ||
1419 // not((W[36]^(W[41]<<2))&(1<<30)) != 0 {
1420 // mask &= ^DV_II_49_0_bit
1421 // }
1422 // }
1423 BTL $0x15, AX
1424 JNC f54_skip
1425 MOVL W_37+148(FP), CX
1426 MOVL W_41+164(FP), DX
1427 SHRL $0x19, DX
1428 XORL DX, CX
1429 ANDL $0x00000008, CX
1430 CMPL CX, $0x00000000
1431 JNE f54_in
1432 MOVL W_36+144(FP), CX
1433 MOVL W_41+164(FP), DX
1434 SHLL $0x02, DX
1435 XORL DX, CX
1436 ANDL $0x40000000, CX
1437 CMPL CX, $0x00000000
1438 JNE f54_in
1439 JMP f54_skip
1440
1441f54_in:
1442 ANDL $0xffdfffff, AX
1443
1444f54_skip:
1445 // if (mask & DV_II_49_2_bit) != 0 {
1446 // if not(not((W[53]^(W[54]<<5))&(1<<6))) != 0 ||
1447 // not(not((W[51]^W[53])&(1<<6))) != 0 ||
1448 // not((W[50]^W[54])&(1<<1)) != 0 ||
1449 // not(not((W[45]^(W[46]<<5))&(1<<6))) != 0 ||
1450 // not(not((W[37]^(W[41]>>25))&(1<<5))) != 0 ||
1451 // not((W[36]^(W[41]>>30))&(1<<0)) != 0 {
1452 // mask &= ^DV_II_49_2_bit
1453 // }
1454 // }
1455 BTL $0x16, AX
1456 JNC f55_skip
1457 MOVL W_53+212(FP), CX
1458 MOVL W_54+216(FP), DX
1459 SHLL $0x05, DX
1460 XORL DX, CX
1461 ANDL $0x00000040, CX
1462 CMPL CX, $0x00000000
1463 JNE f55_in
1464 MOVL W_51+204(FP), CX
1465 MOVL W_53+212(FP), DX
1466 XORL DX, CX
1467 ANDL $0x00000040, CX
1468 CMPL CX, $0x00000000
1469 JNE f55_in
1470 MOVL W_50+200(FP), CX
1471 MOVL W_54+216(FP), DX
1472 XORL DX, CX
1473 ANDL $0x00000002, CX
1474 NEGL CX
1475 CMPL CX, $0x00000000
1476 JE f55_in
1477 MOVL W_45+180(FP), CX
1478 MOVL W_46+184(FP), DX
1479 SHLL $0x05, DX
1480 XORL DX, CX
1481 ANDL $0x00000040, CX
1482 CMPL CX, $0x00000000
1483 JNE f55_in
1484 MOVL W_37+148(FP), CX
1485 MOVL W_41+164(FP), DX
1486 SHRL $0x19, DX
1487 XORL DX, CX
1488 ANDL $0x00000020, CX
1489 CMPL CX, $0x00000000
1490 JNE f55_in
1491 MOVL W_36+144(FP), CX
1492 MOVL W_41+164(FP), DX
1493 SHRL $0x1e, DX
1494 XORL DX, CX
1495 ANDL $0x00000001, CX
1496 NEGL CX
1497 CMPL CX, $0x00000000
1498 JE f55_in
1499 JMP f55_skip
1500
1501f55_in:
1502 ANDL $0xffbfffff, AX
1503
1504f55_skip:
1505 // if (mask & DV_II_50_0_bit) != 0 {
1506 // if not((W[55]^W[58])&(1<<29)) != 0 ||
1507 // not(not((W[38]^(W[42]>>25))&(1<<3))) != 0 ||
1508 // not((W[37]^(W[42]<<2))&(1<<30)) != 0 {
1509 // mask &= ^DV_II_50_0_bit
1510 // }
1511 // }
1512 BTL $0x17, AX
1513 JNC f56_skip
1514 MOVL W_55+220(FP), CX
1515 MOVL W_58+232(FP), DX
1516 XORL DX, CX
1517 ANDL $0x20000000, CX
1518 NEGL CX
1519 CMPL CX, $0x00000000
1520 JE f56_in
1521 MOVL W_38+152(FP), CX
1522 MOVL W_42+168(FP), DX
1523 SHRL $0x19, DX
1524 XORL DX, CX
1525 ANDL $0x00000008, CX
1526 CMPL CX, $0x00000000
1527 JNE f56_in
1528 MOVL W_37+148(FP), CX
1529 MOVL W_42+168(FP), DX
1530 SHRL $0x02, DX
1531 XORL DX, CX
1532 ANDL $0x40000000, CX
1533 NEGL CX
1534 CMPL CX, $0x00000000
1535 JE f56_in
1536 JMP f56_skip
1537
1538f56_in:
1539 ANDL $0xff7fffff, AX
1540
1541f56_skip:
1542 // if (mask & DV_II_50_2_bit) != 0 {
1543 // if not(not((W[54]^(W[55]<<5))&(1<<6))) != 0 ||
1544 // not(not((W[52]^W[54])&(1<<6))) != 0 ||
1545 // not((W[51]^W[55])&(1<<1)) != 0 ||
1546 // not((W[45]^W[47])&(1<<1)) != 0 ||
1547 // not(not((W[38]^(W[42]>>25))&(1<<5))) != 0 ||
1548 // not((W[37]^(W[42]>>30))&(1<<0)) != 0 {
1549 // mask &= ^DV_II_50_2_bit
1550 // }
1551 // }
1552 BTL $0x18, AX
1553 JNC f57_skip
1554 MOVL W_54+216(FP), CX
1555 MOVL W_55+220(FP), DX
1556 SHLL $0x05, DX
1557 XORL DX, CX
1558 ANDL $0x00000040, CX
1559 CMPL CX, $0x00000000
1560 JNE f57_in
1561 MOVL W_52+208(FP), CX
1562 MOVL W_54+216(FP), DX
1563 XORL DX, CX
1564 ANDL $0x00000040, CX
1565 CMPL CX, $0x00000000
1566 JNE f57_in
1567 MOVL W_51+204(FP), CX
1568 MOVL W_55+220(FP), DX
1569 XORL DX, CX
1570 ANDL $0x00000002, CX
1571 NEGL CX
1572 CMPL CX, $0x00000000
1573 JE f57_in
1574 MOVL W_45+180(FP), CX
1575 MOVL W_47+188(FP), DX
1576 XORL DX, CX
1577 ANDL $0x00000002, CX
1578 NEGL CX
1579 CMPL CX, $0x00000000
1580 JE f57_in
1581 MOVL W_38+152(FP), CX
1582 MOVL W_42+168(FP), DX
1583 SHRL $0x19, DX
1584 XORL DX, CX
1585 ANDL $0x00000020, CX
1586 CMPL CX, $0x00000000
1587 JNE f57_in
1588 MOVL W_37+148(FP), CX
1589 MOVL W_42+168(FP), DX
1590 SHRL $0x1e, DX
1591 XORL DX, CX
1592 ANDL $0x00000001, CX
1593 NEGL CX
1594 CMPL CX, $0x00000000
1595 JE f57_in
1596 JMP f57_skip
1597
1598f57_in:
1599 ANDL $0xfeffffff, AX
1600
1601f57_skip:
1602 // if (mask & DV_II_51_0_bit) != 0 {
1603 // if not(not((W[39]^(W[43]>>25))&(1<<3))) != 0 ||
1604 // not((W[38]^(W[43]<<2))&(1<<30)) != 0 {
1605 // mask &= ^DV_II_51_0_bit
1606 // }
1607 // }
1608 BTL $0x19, AX
1609 JNC f58_skip
1610 MOVL W_39+156(FP), CX
1611 MOVL W_43+172(FP), DX
1612 SHRL $0x19, DX
1613 XORL DX, CX
1614 ANDL $0x00000008, CX
1615 CMPL CX, $0x00000000
1616 JNE f58_in
1617 MOVL W_38+152(FP), CX
1618 MOVL W_43+172(FP), DX
1619 SHLL $0x02, DX
1620 XORL DX, CX
1621 ANDL $0x40000000, CX
1622 NEGL CX
1623 CMPL CX, $0x00000000
1624 JE f58_in
1625 JMP f58_skip
1626
1627f58_in:
1628 ANDL $0xfdffffff, AX
1629
1630f58_skip:
1631 // if (mask & DV_II_51_2_bit) != 0 {
1632 // if not(not((W[55]^(W[56]<<5))&(1<<6))) != 0 ||
1633 // not(not((W[53]^W[55])&(1<<6))) != 0 ||
1634 // not((W[52]^W[56])&(1<<1)) != 0 ||
1635 // not((W[46]^W[48])&(1<<1)) != 0 ||
1636 // not(not((W[39]^(W[43]>>25))&(1<<5))) != 0 ||
1637 // not((W[38]^(W[43]>>30))&(1<<0)) != 0 {
1638 // mask &= ^DV_II_51_2_bit
1639 // }
1640 // }
1641 BTL $0x1a, AX
1642 JNC f59_skip
1643 MOVL W_55+220(FP), CX
1644 MOVL W_56+224(FP), DX
1645 SHLL $0x05, DX
1646 XORL DX, CX
1647 ANDL $0x00000040, CX
1648 CMPL CX, $0x00000000
1649 JNE f59_in
1650 MOVL W_53+212(FP), CX
1651 MOVL W_55+220(FP), DX
1652 XORL DX, CX
1653 ANDL $0x00000040, CX
1654 CMPL CX, $0x00000000
1655 JNE f59_in
1656 MOVL W_52+208(FP), CX
1657 MOVL W_56+224(FP), DX
1658 XORL DX, CX
1659 ANDL $0x00000002, CX
1660 NEGL CX
1661 CMPL CX, $0x00000000
1662 JE f59_in
1663 MOVL W_46+184(FP), CX
1664 MOVL W_48+192(FP), DX
1665 XORL DX, CX
1666 ANDL $0x00000002, CX
1667 NEGL CX
1668 CMPL CX, $0x00000000
1669 JE f59_in
1670 MOVL W_39+156(FP), CX
1671 MOVL W_43+172(FP), DX
1672 SHRL $0x19, DX
1673 XORL DX, CX
1674 ANDL $0x00000020, CX
1675 CMPL CX, $0x00000000
1676 JNE f59_in
1677 MOVL W_38+152(FP), CX
1678 MOVL W_43+172(FP), DX
1679 SHRL $0x1e, DX
1680 XORL DX, CX
1681 ANDL $0x00000001, CX
1682 NEGL CX
1683 CMPL CX, $0x00000000
1684 JE f59_in
1685 JMP f59_skip
1686
1687f59_in:
1688 ANDL $0xfbffffff, AX
1689
1690f59_skip:
1691 // if (mask & DV_II_52_0_bit) != 0 {
1692 // if not(not((W[59]^W[60])&(1<<29))) != 0 ||
1693 // not(not((W[40]^(W[44]>>25))&(1<<3))) != 0 ||
1694 // not(not((W[40]^(W[44]>>25))&(1<<4))) != 0 ||
1695 // not((W[39]^(W[44]<<2))&(1<<30)) != 0 {
1696 // mask &= ^DV_II_52_0_bit
1697 // }
1698 // }
1699 BTL $0x1b, AX
1700 JNC f60_skip
1701 MOVL W_59+236(FP), CX
1702 MOVL W_60+240(FP), DX
1703 XORL DX, CX
1704 ANDL $0x20000000, CX
1705 CMPL CX, $0x00000000
1706 JNE f60_in
1707 MOVL W_40+160(FP), CX
1708 MOVL W_44+176(FP), DX
1709 SHRL $0x19, DX
1710 XORL DX, CX
1711 ANDL $0x00000008, CX
1712 CMPL CX, $0x00000000
1713 JNE f60_in
1714 MOVL W_40+160(FP), CX
1715 MOVL W_44+176(FP), DX
1716 SHRL $0x19, DX
1717 XORL DX, CX
1718 ANDL $0x00000010, CX
1719 CMPL CX, $0x00000000
1720 JNE f60_in
1721 MOVL W_39+156(FP), CX
1722 MOVL W_44+176(FP), DX
1723 SHLL $0x02, DX
1724 XORL DX, CX
1725 ANDL $0x40000000, CX
1726 NEGL CX
1727 CMPL CX, $0x00000000
1728 JE f60_in
1729 JMP f60_skip
1730
1731f60_in:
1732 ANDL $0xf7ffffff, AX
1733
1734f60_skip:
1735 // if (mask & DV_II_53_0_bit) != 0 {
1736 // if not((W[58]^W[61])&(1<<29)) != 0 ||
1737 // not(not((W[57]^(W[61]>>25))&(1<<4))) != 0 ||
1738 // not(not((W[41]^(W[45]>>25))&(1<<3))) != 0 ||
1739 // not(not((W[41]^(W[45]>>25))&(1<<4))) != 0 {
1740 // mask &= ^DV_II_53_0_bit
1741 // }
1742 // }
1743 BTL $0x1c, AX
1744 JNC f61_skip
1745 MOVL W_58+232(FP), CX
1746 MOVL W_61+244(FP), DX
1747 XORL DX, CX
1748 ANDL $0x20000000, CX
1749 NEGL CX
1750 CMPL CX, $0x00000000
1751 JE f61_in
1752 MOVL W_57+228(FP), CX
1753 MOVL W_61+244(FP), DX
1754 SHRL $0x19, DX
1755 XORL DX, CX
1756 ANDL $0x00000010, CX
1757 CMPL CX, $0x00000000
1758 JNE f61_in
1759 MOVL W_41+164(FP), CX
1760 MOVL W_45+180(FP), DX
1761 SHRL $0x19, DX
1762 XORL DX, CX
1763 ANDL $0x00000008, CX
1764 CMPL CX, $0x00000000
1765 JNE f61_in
1766 MOVL W_41+164(FP), CX
1767 MOVL W_45+180(FP), DX
1768 SHRL $0x19, DX
1769 XORL DX, CX
1770 ANDL $0x00000010, CX
1771 CMPL CX, $0x00000000
1772 JNE f61_in
1773 JMP f61_skip
1774
1775f61_in:
1776 ANDL $0xefffffff, AX
1777
1778f61_skip:
1779 // if (mask & DV_II_54_0_bit) != 0 {
1780 // if not(not((W[58]^(W[62]>>25))&(1<<4))) != 0 ||
1781 // not(not((W[42]^(W[46]>>25))&(1<<3))) != 0 ||
1782 // not(not((W[42]^(W[46]>>25))&(1<<4))) != 0 {
1783 // mask &= ^DV_II_54_0_bit
1784 // }
1785 // }
1786 BTL $0x1d, AX
1787 JNC f62_skip
1788 MOVL W_58+232(FP), CX
1789 MOVL W_62+248(FP), DX
1790 SHRL $0x19, DX
1791 XORL DX, CX
1792 ANDL $0x00000010, CX
1793 CMPL CX, $0x00000000
1794 JNE f62_in
1795 MOVL W_42+168(FP), CX
1796 MOVL W_46+184(FP), DX
1797 SHRL $0x19, DX
1798 XORL DX, CX
1799 ANDL $0x00000008, CX
1800 CMPL CX, $0x00000000
1801 JNE f62_in
1802 MOVL W_42+168(FP), CX
1803 MOVL W_46+184(FP), DX
1804 SHRL $0x19, DX
1805 XORL DX, CX
1806 ANDL $0x00000010, CX
1807 CMPL CX, $0x00000000
1808 JNE f62_in
1809 JMP f62_skip
1810
1811f62_in:
1812 ANDL $0xdfffffff, AX
1813
1814f62_skip:
1815 // if (mask & DV_II_55_0_bit) != 0 {
1816 // if not(not((W[59]^(W[63]>>25))&(1<<4))) != 0 ||
1817 // not(not((W[57]^(W[59]>>25))&(1<<4))) != 0 ||
1818 // not(not((W[43]^(W[47]>>25))&(1<<3))) != 0 ||
1819 // not(not((W[43]^(W[47]>>25))&(1<<4))) != 0 {
1820 // mask &= ^DV_II_55_0_bit
1821 // }
1822 // }
1823 BTL $0x1e, AX
1824 JNC f63_skip
1825 MOVL W_59+236(FP), CX
1826 MOVL W_63+252(FP), DX
1827 SHRL $0x19, DX
1828 XORL DX, CX
1829 ANDL $0x00000010, CX
1830 CMPL CX, $0x00000000
1831 JNE f63_in
1832 MOVL W_57+228(FP), CX
1833 MOVL W_59+236(FP), DX
1834 SHRL $0x19, DX
1835 XORL DX, CX
1836 ANDL $0x00000010, CX
1837 CMPL CX, $0x00000000
1838 JNE f63_in
1839 MOVL W_43+172(FP), CX
1840 MOVL W_47+188(FP), DX
1841 SHRL $0x19, DX
1842 XORL DX, CX
1843 ANDL $0x00000008, CX
1844 CMPL CX, $0x00000000
1845 JNE f63_in
1846 MOVL W_43+172(FP), CX
1847 MOVL W_47+188(FP), DX
1848 SHRL $0x19, DX
1849 XORL DX, CX
1850 ANDL $0x00000010, CX
1851 CMPL CX, $0x00000000
1852 JNE f63_in
1853 JMP f63_skip
1854
1855f63_in:
1856 ANDL $0xbfffffff, AX
1857
1858f63_skip:
1859 // if (mask & DV_II_56_0_bit) != 0 {
1860 // if not(not((W[60]^(W[64]>>25))&(1<<4))) != 0 ||
1861 // not(not((W[44]^(W[48]>>25))&(1<<3))) != 0 ||
1862 // not(not((W[44]^(W[48]>>25))&(1<<4))) != 0 {
1863 // mask &= ^DV_II_56_0_bit
1864 // }
1865 // }
1866 BTL $0x1f, AX
1867 JNC f64_skip
1868 MOVL W_60+240(FP), CX
1869 MOVL W_64+256(FP), DX
1870 SHRL $0x19, DX
1871 XORL DX, CX
1872 ANDL $0x00000010, CX
1873 CMPL CX, $0x00000000
1874 JNE f64_in
1875 MOVL W_44+176(FP), CX
1876 MOVL W_48+192(FP), DX
1877 SHRL $0x19, DX
1878 XORL DX, CX
1879 ANDL $0x00000008, CX
1880 CMPL CX, $0x00000000
1881 JNE f64_in
1882 MOVL W_44+176(FP), CX
1883 MOVL W_48+192(FP), DX
1884 SHRL $0x19, DX
1885 XORL DX, CX
1886 ANDL $0x00000010, CX
1887 CMPL CX, $0x00000000
1888 JNE f64_in
1889 JMP f64_skip
1890
1891f64_in:
1892 ANDL $0x7fffffff, AX
1893
1894f64_skip:
1895end:
1896 MOVL AX, ret+320(FP)
1897 RET